Today, we announced that IonQ Forte, our flagship, commercially available quantum computer, successfully passed the #AQ 35 benchmark suite. #AQ 35 was IonQ’s technical target for 2024 and we are excited to have achieved it a year ahead of schedule. This blog post will dive into the technical progress made since we achieved #AQ 29 seven months early in June 2023.
IonQ Performance Roadmap
IonQ’s goal is to build quantum computers that can deliver value to our customers by successfully executing the applications they care about. As such, our roadmap is based on achieving higher and higher performance on an application based benchmark that is representative of the most promising, commercial algorithmic approaches. When we shared our performance roadmap for the first time, no such application based benchmark existed - and so IonQ built on the work of the largest quantum industry consortium, the QED-C - to develop a benchmark called Algorithmic Qubits (#AQ). Since then, we have been laser focused on optimizing across the entire quantum computing stack to attain the ambitious targets laid out in our roadmap, knowing that the higher the #AQ a system offers, the more commercial value we can deliver to our partners and customers. IonQ Forte, which was made commercially available for the first time at #AQ 29, brings us one step closer to the era of enterprise-grade quantum computing - where quantum computers can offer value to enterprises investing in quantum application development.
IonQ Forte, an Innovative Approach to Trapped Ion Quantum Computing
When we announced Forte in 2022, one of its key differentiating features was software reconfigurability. By this, we meant that we can dynamically reconfigure elements in Forte instead of requiring fabrication in other architectures. For example, qubit count can be tuned via a flexible surface ion trap, and ions at different locations can be addressed dynamically via Forte’s acousto-optic deflectors (AODs), which enable the precise steering of control lasers. As such, Forte was designed from the beginning to be able to push the boundaries of performance through a combination of hardware and software upgrades. First with #AQ 29, and now with #AQ 35, IonQ is positioning Forte as a system that is capable of running wider circuits while maintaining high gate fidelity and all-to-all qubit connectivity.
At IonQ, when we think about performance of a quantum computer, we think in terms of the end-to-end customer experience. We want to make sure that applications are optimized for our hardware, that the hardware delivers our expected high performance, and that appropriate error mitigation is applied to provide maximum value. This means that performance naturally breaks into three different factors:
Application optimization: First, we make sure that the application of interest is implemented using a best-in-class algorithm for the problem a customer is trying to solve, and that it is compiled as efficiently as possible for our unique machine hardware. This factor is all about making sure that the application is expressed as efficiently as possible. For example, if we can use a classical computer to efficiently reduce the number of two qubit gates that are performed to do an equivalent quantum circuit, this can lead to dramatically better performance. Another factor that makes a huge difference here is the connectivity of the quantum processor: quantum computers in which more qubits can be coupled together support more efficient application compilation than those with more limited connectivities.
Hardware optimization: Once the application is as efficient as we know how to make it, we need to run it on quantum hardware. This factor is all about getting as much raw performance from the hardware as possible, and is frequently characterized in terms of the number of physical qubits and single- and two-qubit gate fidelities. Gate fidelities aren’t the whole story though: we also care about unintentional qubit interactions (crosstalk), time drift of the calibration state of the machine, and decoherence times. At IonQ, we employ advanced techniques in the design and operation of our systems to improve the hardware performance. For example, we use diagnostic characterization to figure out where the problems lie, and fix them via combinations of hardware improvements, pulse-level control optimization, and gate-level techniques like dynamical decoupling.
Error mitigation: Now that we’ve done as much as we can optimizing the application and hardware, we still have one step left to deliver the most customer value. Error mitigation is a broad term referring to data processing techniques that can boost the effective performance of noisy quantum circuit operations. Some error mitigation techniques such as zero noise extrapolation, scale exponentially in the number of experimental samples. Others, such as sharpening (also known as plurality voting) do not require additional samples, but can degrade performance of some circuits. While error mitigation does not scale indefinitely, it can extend the reach of today’s quantum processors considerably, and as stated before, we want to be able to provide our customers maximum value.
Improvements along any of these three factors can move the needle on realized customer value and IonQ’s strategy for attaining our #AQ targets has always been anchored in improvements across all three factors. Understanding what factor is driving increases can help our customers better understand how #AQ improvements will translate to a specific application. Application based benchmarking is unique in its ability to reward improvements across the entire quantum computing stack - which is exactly how our customers will experience our quantum computers.
Pushing IonQ Forte From #AQ 29 to #AQ 35
In the case of our #AQ 35 announcement, two critical factors contributed: increased qubits (hardware optimization) and more efficient compilation (application optimization). Let’s dive into each of these now.
IonQ Forte underwent two main hardware optimizations to improve performance and scale. First, the qubit count was increased from 30 to 36. Thanks to optimizations made to the configurable AOD, these additional qubits were added without impacting gate fidelities or connectivity. This is a huge win, since the computational state space of the original 30 qubits has dimension about 1 billion, while 36 qubits has dimension over 68 billion. Second, new detection optics were designed and installed to accurately image and measure the longer qubit chain.
But hardware enhancements are only one part of the story: we also boosted the performance of our compiler. In our #AQ 29 results, we were depth-limited by two circuit families in the #AQ repository: Monte Carlo (MC) and Amplitude Estimation (AE) circuits. To pass #AQ 35, we need to pass the MC and AE benchmark circuits on 7 qubits, which in their Qiskit specification require 982 and 868 two-qubit gates, respectively. The compiler used to pass #AQ 29 optimized these circuits to reduce the MC gates by 46% and the AE gates by 32%. More recently, by applying novel compilation strategies that efficiently search for repeated small-qubit blocks within a circuit, the #AQ 35 compiler reduced the two-qubit gate counts for MC by 97% to just 26 gates and by 95% to 36 gates for AE. It’s important to note that, even after extensive compiler optimization, we still need to run deep circuits. In particular, our AQ #35 volume is bounded by Phase Estimation on 35 qubits (243 two-qubit gates), Hamiltonian Simulation on 35 qubits (306 two-qubit gates), and Quantum Fourier Transform on 26 qubits (335 two-qubit gates).
The #AQ 35 compiler is highly effective on the MC and AE circuits and we expect that additional circuits run by our customers will benefit as well from this compilation innovation. While we do not intend to suggest that all applications will scale through the #AQ 35 compiler alone, these results are proof that detailed application optimization can be beneficial and are worth continued investment. We are excited to announce that these specific optimizations will soon be turned on for IonQ’s default cloud compiler, so customers can take advantage of these performance gains with no additional cost or effort.
The Path Forward and #AQ 64
We believe application-based benchmarks are the best way to understand how a system will perform against actual problems, and therefore we think they are the most important, and useful, way to benchmark systems. To ensure we are putting real world customer problems at the center of our research and development and product strategy, we will continue to invest in application-based benchmarks. We plan to release a technical manuscript describing more of the details of our #AQ 35 achievement in the next couple of months.
While we continue to work in an open and collaborative way to help our customers benchmark system performance, our eyes are fixed on the next target on our hardware roadmap: #AQ 64. We believe #AQ 64 will be a turning point for the industry, where circuits that are large enough and complex enough to create commercial value are able to be successfully executed on IonQ hardware. The attainment of #AQ 64 will be dependent on hardware optimizations driven by our transition to Barium qubits and the deployment of reconfigurable multi-core quantum architectures enabled by new IonQ trap technology. In addition, software optimization and error mitigation will continue to improve algorithmic results as we work to unlock even more commercial value for our customers.
While we are excited about reaching our technical target for 2024 a year ahead of schedule, we are committed to remaining ambitious in our hardware, software and application development for the rest of 2024. We hope you will join us on our journey by getting access to IonQ Forte to solve your problems, subscribing to our email list, or exp